Lower Bounds on the Area Complexity of Boolean Circuits

Hromkovif, J., S.A. Loikin, A.I. Rybko, A.A. Sapoienko and N.A. Skalikova, Lower bounds on the area complexity of Boolean circuits, Theoretical Computer Science 97 (1992) 2855300. The layout area of Boolean circuits is considered as a complexity measure of Boolean functions. Introducing the communication complexity of Boolean circuits and proving that this communication complexity squared provides a lower bound on the area complexity, one obtains a powerful lower-bound technique for the area complexity of Boolean functions. Using this technique, the highest-known lower bound fi(ns’*) on the layout area of any Boolean circuit computing a specific Boolean function is improved to Q(n2). An R(n’/(log, n)‘) lower bound on the number of gates of planar Boolean circuits computing a specific one-output Boolean function is a direct consequence of this result. The circuit communication complexity that we introduce is related to the area of Boolean circuits that have all input vertices on the border of their layout, and also to the three-dimensional layout of Boolean circuits.